The present invention relates generally to the testing of interfaces between digital integrated components, and more particularly, to testing one or more interfaces associated with a digital integrated circuit while at least one or more other interfaces associated with the digital integrated circuit continues to operate in a normal operation mode.
The sophistication of a present-day electronic system is a result of complex functions handled by digital integrated circuits making up the electronic system. Digital integrated circuits comprise the majority of electronic circuits in computers and other digital electronic products. Digital integrated circuits can be configured, for example, as a central processing unit (CPU), a programmable logic array (PLA), an application specific integrated circuit (ASIC), or a digital signal processor (DSP). Both the sophistication and speed of operation of these digital integrated circuits have rapidly increased due to improvements in integrated circuit manufacturing technologies resulting in smaller and faster devices. Replacing electronic components, such as a digital integrated circuit within a computer or digital electronic product, has become a standard practice. In addition, upgrading a computer or digital electronic product by installing additional hardware, such as digital integrated circuits, has become standard practices.
Once a particular digital integrated circuit has been installed, either for replacement or upgrade purposes, it is important to ensure that the various interfaces of the digital integrated circuit are properly connected with other digital integrated circuits or electronic components. Two test methods are commonly used in the electronics industry to test the interface between two or more digital integrated circuits, which are used, for example, in a computer system. The first test method utilizes a functional test approach, in which the interface in question is exercised using a software program which forces the associated digital integrated circuits to interact via the interface being tested in a normal, standard manner. In other words, the normal interaction between the associated digital integrated circuits must be triggered. The functional test method has several disadvantages, in that the test is usually difficult to write, having unknown test coverage, and frequently disrupts the normal use of the interface and all integrated circuits on the interface. More specifically, the interface may be infrequently used or may only be used in an error situation. Also, the interface may facilitate a destructive occurrence. Thus, the software program will override the normal function of the interface such that the interface provides a signal which creates an undesireous or destructive result to the overall system.
The second common test method for testing the interface between two digital integrated circuits is a boundary scan method. This method is standardized by IEEE Standard 1149.1b (1994) IEEE Standard Test Access Port and Boundary Scan Architecture (supplement to IEEE Standard 1149.1 (1990) and IEEE Standard 1149.1a (1993)). The IEEE Standard 1149.1 (1990) and any past or future revisions, including the referenced revisions made in 1993 and 1994, are hereby incorporated by reference in their entirety. The boundary scan method, as standardized, is known in the art as the cornerstone for interface testing procedures in this field.
In the boundary scan method, all of the input pins (also called ports or pads) and output pins of a digital integrated circuit are placed under control of test software. Test patterns are driven over the one or more interfaces of the digital integrated circuit by a test software control via boundary scan cells interconnected between the logic and the pins of the digital integrated circuit. Such test patterns are easily machine generated having known test coverage. The test patterns are easily applied and the results easily evaluated. However, since all input and output pins are involved in the boundary scan test, they are not capable of normal operation. Thus, for the boundary scan test to be executed, all normal operation of the integrated circuit under the boundary scan test is stopped. This is an undesireous effect in that with the complex technology of integrated circuit designs, various integrated circuits are interconnected. Under the boundary scan test, all interfaces between the particular digital integrated circuit being tested and any other integrated circuit are overridden, and therefore not operating under normal conditions, but rather operating under test conditions. Thus, by testing the interfaces of a single digital integrated circuit, an entire network of digital integrated circuits may cease to operate under a normal mode, such that a test mode can be provided.
Therefore, there is a need for a testing system and method which can reliably test one or more interfaces of a digital integrated circuit, while permitting other interfaces of the digital integrated circuit to operate under normal conditions, such that when testing some of the interfaces of an integrated circuit, an entire network of interfaces between numerous integrated circuits is not inhibited.
The present invention provides a system and method for testing at least one interface of a digital integrated circuit while at least one other interface of the digital integrated circuit operates in a normal operation mode. Each interface has at least one boundary scan cell, each boundary scan cell electrically coupled to a pin of the digital integrated circuit. Each interface includes a mode input.
The method of the present invention includes selectively categorizing at least one interface into a first category. At least one other interface is selectively categorized into a second category. A first mode signal is provided to the interfaces categorized into the test mode category such that the interfaces categorized into the test mode category operate in a test mode. A second mode signal is provided to the interfaces categorized into the normal operation mode category such that the second set of boundary scan cells operates in the normal operation mode.
In one embodiment, the steps of selectively categorizing the first and second interfaces is further defined by a controller, such as a Test Access Port. This controller facilitates selectively categorizing a particular interface into one of the first or second categories. Additionally, the step of providing the first mode signal further includes providing a test mode signal to the interfaces categorized into the test mode category such that a first subset of the boundary scan cells within the interfaces categorized into the test mode category associated with an output pin of the digital integrated circuit provides a test output signal. In another embodiment of the invention, the method further includes providing a boundary scan signal to each boundary scan cell.
In yet another embodiment of the invention, a system is provided for testing at least one interface of a digital integrated circuit categorized into a test mode category while at least another interface of the digital integrated circuit categorized into a normal operation mode category operates in a normal operation mode. The system includes a plurality of boundary scan cells, each boundary scan cell electrically coupled to a pin of the digital integrated circuit. Each interface includes at least one boundary scan cell. A controller is electrically coupled to each interface and capable of providing either a test mode signal or a normal operation mode signal to each interface such that the boundary scan cells of the at least one interface operate in a test mode and the boundary scan cells of the at least one other interface operate in a normal operation mode.